Routing decisions made in the last weeks of a layout often determine whether a board works reliably or becomes a debugging project. The following questions and answers cover the practical issues hardware teams raise most often, from high-frequency signal behavior to grounding strategy, stackup selection and thermal layout. The guidance is general and should be checked against your own component data and fabrication capabilities.

High-frequency routing and via strategy

When routing high-frequency signals, three points matter most: impedance matching of the signal line, spatial separation from other traces, and, for digital high-frequency signals, the use of differential pairs. Differential routing is generally more robust than single-ended routing in these cases.

Trace density often forces more vias, which can affect electrical performance. For low-frequency signals, vias are not a major concern; for high-frequency signals, minimize them. If the routing demand is high, consider moving to a multilayer board rather than adding vias.

Decoupling capacitors are not a case of more is better. They need the right value in the right location. For example, supply ports of analog devices require decoupling, and different capacitor values are used to filter spurious signals at different frequencies.

A good board can be judged by a few broad criteria: sensible placement, adequate power trace redundancy, controlled high-frequency impedance, and clean low-frequency routing.

Through holes, blind vias and buried vias

Blind and buried vias are effective ways to increase density in multilayer boards, reduce layer count and shrink board dimensions, and they significantly reduce the number of plated through holes. In practice, however, through holes are easier to fabricate and lower in cost, so most designs use through holes. The choice should be driven by density and performance requirements, not by preference alone.

Mixed-signal grounding and power partitioning

In mixed analog-digital systems, one common recommendation is to split the power plane while keeping the ground plane as a solid copper pour. Another is to split both power and ground planes and connect the different grounds at the power entry point, although this lengthens the signal return path. The right choice depends on the signal content.

If there are high-frequency signals above 20 MHz, and both their length and number are significant, allocate at least two layers to the analog high-frequency section: one signal layer and one large ground plane, with enough vias from the signal layer to ground. This serves three purposes:

  • It provides a complete transmission medium and impedance matching for the analog signal.
  • The ground plane isolates the analog signal from other digital signals.
  • The ground return loop stays small because many vias connect to a large plane.

When a signal input connector sits at one edge of the board and the MCU at the other, the placement of the regulator deserves thought. If the input connector carries analog signals, the power layout should avoid disturbing analog signal integrity. Consider whether the regulator is clean and low-ripple, since analog sections are sensitive to supply quality. In high-precision designs, separate the analog and digital supplies. For the digital section, minimize any impact on the analog circuitry.

For multi-ASIC high-speed signal chains that include both analog and digital grounds, there is no universal answer on whether to split the ground. In general, consult the device datasheet; mixed-signal chip vendors often recommend a specific grounding scheme, some favoring a common ground and others isolation, depending on the chip design.

Length matching and serpentine routing

Length matching becomes necessary when timing between signals must be controlled. For differential pairs, one way to estimate the limit is to consider a sine wave: if the length difference equals half the transmission wavelength, the phase difference reaches 180 degrees and the two signals cancel completely. That length difference is the maximum; in practice the mismatch must be smaller.

Serpentine routing serves different purposes depending on the application. On computer boards it acts as a filter inductor and impedance-matching element to improve immunity, and appears on clock signals such as PCI-Clk, AGP-Clk, IDE and DIMM lines. On ordinary boards it can also form an inductor coil, for example in a 2.4G radio. Where strict equal length is required, as in high-speed digital boards, serpentine routing keeps delay differences within a range so that the system reads valid data within the same clock cycle; if the delay difference exceeds one clock cycle, data from the next cycle can be read incorrectly.

In architectures that use many parallel high-speed links at frequencies such as 233 MHz, strict length matching is required to eliminate timing hazards, and serpentine routing is the only practical solution. A common rule is to keep the delay difference below one quarter of the clock period. Delay per unit length is fixed and depends on trace width, length, copper thickness and layer structure. Long traces increase distributed capacitance and inductance and degrade signal quality, so clock IC pins are usually terminated. Note that serpentine routing does not act as an inductor in this context; inductance would phase-shift the higher harmonics of the rising edge and worsen signal quality. Keep serpentine spacing at least twice the trace width. The shorter the rise time, the more sensitive the signal is to distributed capacitance and inductance. In some special circuits, serpentine routing acts as a distributed LC filter.

EMC/EMI and RF transmission lines

EMI/EMC must be considered from the first placement decision: device positions, stackup arrangement, routing of important connections and component selection. Keep clock generators away from external connectors, route high-speed signals on inner layers with impedance matching and a continuous reference plane to reduce reflections, and use devices with low slew rate to limit high-frequency content. When selecting decoupling and bypass capacitors, check that their frequency response suits the need to reduce power-plane noise. Keep the return path of high-frequency currents short so that loop area, and therefore loop impedance, is small, reducing radiation. Splitting ground planes can also confine high-frequency noise. Finally, choose chassis ground points between the PCB and enclosure carefully.

For RF broadband circuits, transmission line design depends on many factors: PCB material parameters, the transmission line model built from those parameters, and device parameters. Impedance matching is usually designed using data supplied by the fabricator, so early engagement with the PCB manufacturer is worthwhile.

Stackup, component packages and layer count

In mixed analog-digital designs with an FPGA or MCU on one side and DACs and amplifiers on the other, several supply voltages are common. Sharing a supply voltage between analog and digital sections is generally not recommended; it complicates layout and debugging. Pay attention to routing and ferrite bead placement if you must share.

For high-speed multilayer boards, package selection is driven mainly by parasitic parameters: smaller packages have lower parasitics. 0402 is common in phone designs, while 0603 is common in general high-speed modules. Equivalent packages from different manufacturers can differ significantly at high frequency, so use high-frequency-specific components at critical locations.

On double-sided boards, whether to route signals or ground first depends on the overall layout; place components first, then route.

The most important consideration in high-speed multilayer design is how signal, power, ground and control lines are assigned to layers. As a rule, analog signals and analog ground should have at least one dedicated layer, and power should also have its own layer.

The choice between 2, 4 and 6 layers is not strictly limited by technology apart from size constraints. Multilayer boards provide a complete ground plane and more signal layers for routing. For a CPU controlling external memory, consider the interface frequency: at higher frequencies a complete ground plane is essential, and signal lines should be length-matched.

Trace widths, noise and thermal layout

Analyzing how routing affects analog signal transmission is difficult, and distinguishing routing-induced noise from op-amp noise is even harder. The practical approach is to minimize noise introduced by layout.

For high-speed multilayer boards, power, ground and signal trace widths depend on the case. At 300 MHz, impedance simulation is required to determine trace width and the spacing to ground. Power trace width depends on current. In mixed-signal boards, ground is usually represented by a full plane rather than a trace, which minimizes return resistance and provides a complete plane beneath signal lines.

Thermal layout starts with identifying heat sources: component heat, heat generated by the PCB itself, and heat transferred from other parts. Components are the dominant source, followed by the board. The goal of thermal design is to keep component and board temperatures within a range where the system works reliably, mainly by reducing heat generation and improving heat dissipation.

What this means for your build

  • Define stackup and layer assignment early, because analog and power layers are difficult to add after routing begins.
  • Minimize vias on high-frequency nets and reserve through holes for cost-sensitive or lower-density designs.
  • Treat decoupling as a placement and value problem, not a capacitor-count problem.
  • Confirm impedance targets and transmission line models with your fabricator before release, especially for RF and high-speed nets.
  • Plan thermal copper and airflow during placement so that heat-generating components are not boxed in later.

Source: compiled from public web sources.